The invention relates generally to digital circuits that clock transmit data, and more specifically to providing a circuit that dynamically adjusts the waveform of an input digital clock whose nominal duty cycle may not be 50% and to output a digital close having a substantially 50% duty cycle such that transmission data errors are reduced.
In the field of digital communication, it is common to provide a printed circuit board (PCB) whereon several integrated circuits (ICs) are mounted. FIG. 1 shows a generic PCB containing several ICs, IC-1, IC-2, IC-3, and a clock circuit (CLOCK), which itself may be an IC. FIG. 1 depicts the various ICs coupled to receive an operating potential VDD. In many applications, it is desired that the clock frequency be as fast as possible such that DATA can be output quickly. As such, there is a need for ever faster clock frequencies and data rates.
FIG. 2A depicts an exemplary waveform for the clock signal (CLOCK) as a function of time. In this example, the logical low voltage magnitude of the clock signal is 0 VDC and the logical high voltage magnitude of the clock is VDD. In FIG. 2A, time THIGH denotes the useful high state portion of the clock signal, and TLOW denotes the useful low state portion of the clock signal. The period of the clock signal is defined as T=THIGH+TLOW=1/f, where f is the frequency in Hz of the clock signal. The duty cycle (D) of the clock waveform can be defined as D=THIGH/T or alternatively as D=DLOW/T. The 0-to-1 state portion of the clock waveform defines the rising edge of the clock, and the 1 to-0 state portion of the clock waveform defines the falling edge. In most digital circuits, ICs change state and data is transmitted at the VDD/2 threshold of the rising or falling edge of the clock waveform transitions. As such, increased clock frequency (f) and data transmission between IC""s dictates that the frequency and duty cycle characteristics of the digital signals be more precisely controlled.
FIG. 2B depicts an exemplary data signal (DATA), for example an output signal from IC2 in FIG. 1. IC1 may be considered a transmitter IC that provides a CLOCK signal and a DATA signal to IC2, which may be considered as a receiver IC. Within IC2, the rising and falling edges of the CLOCK signal from IC1 may be used to xe2x80x9clatchxe2x80x9d DATA from IC1 into IC2. The time required for the DATA to arrive at IC2 before the CLOCK signal is present is commonly referred to as the setup time (TSU). Importantly, if DATA should arrive at IC2 too early, at a time less than a certain minimum time TSUM, the DATA can be lost, or latched in incorrectly. The amount of time for the DATA to be held after the CLOCK rising edge is commonly referred to as the hold time (Th). If DATA is removed too soon, e.g., less than a certain time THM, then again DATA can be lost or latched into IC2 in error. Thus, TSUM and THM represent the minimum setup time and hold time for error free data transmission.
Thus there is a need for a mechanism and method to achieve substantially error free data transmission in a digital circuit that clocks transmit data. Preferably such mechanism and method should ensure that the minimum setup and hold timing requirements are always met, even when the input clock duty cycle is not precisely 50%.
The present invention provides such a mechanism and method.
A digital clock adaptive duty cycle circuit receives an input clock CLKIN having duty cycle of close to 50%, and outputs a CLK signal (and its complement CLKB) whose duty cycle may be continuously and automatically varied to ensure that output duty cycle is 50%, precise to within about xc2x10.1%. The overall circuit includes a duty cycle adjustor (DCA) unit that includes preferably an odd number of inverter stages. Preferably at least two of the inverter stages include devices, e.g., MOS transistors, that have a parameter (e.g., threshold voltage VTH) that can be varied as a function of a control voltage VC to affect the duty cycle of the inverter signal output by the inverter. The effect of VTH variation within each inverter stage is to vary the duty cycle of the clock signal output from the inverter stage, and thus from the DCA unit itself. The DCA output signal preferably is converted from a single-ended to a differential signal pair, CLK and its complement CLKB. The differential signal pair is low pass filtered and input differentially to an operational amplifier. The output of the operation amplifier is fedback to the DCA unit as control voltage VC.
The ability to receive an input clock whose duty cycle may not be exactly 50%, and to dynamically ensure an output CLK signal with a precise 50% duty cycle enables data to be clocked or latch-transferred from IC stage to IC stage substantially error free, even if IC stage setup time varies. The ability to ensure substantially error free data transfer is maintained, even as clock frequency is increased.